Cell (processor)
[10] In March 2007, IBM announced that the 65 nm version of Cell/BE was in production at its plant (at the time, now GlobalFoundries') in East Fishkill, New York,[10][11] with Bandai Namco Entertainment using the Cell/BE processor for their 357 arcade board as well as the subsequent 369.[20] In the PlayStation 3, one SPE is locked-out during the test process, a practice which helps to improve manufacturing yields, and another one is reserved for the OS, leaving 6 free SPEs to be used by games' code.[19] The introductory design is fabricated using a 90 nm SOI process, with initial volume production slated for IBM's facility in East Fishkill, New York.[22] Mercury has since then released blades, conventional rack servers and PCI Express accelerator boards with Cell processors.To make the best of EIB, and to overlap computation and data transfer, each of the nine processing elements (PPE and SPEs) is equipped with a DMA engine.[28] The PowerXCell 8i powered super computers also dominated all of the top 6 "greenest" systems in the Green500 list, with highest MFLOPS/Watt ratio supercomputers in the world.The PPE[32][33][34] is the PowerPC based, dual-issue in-order two-way simultaneous-multithreaded CPU core with a 23-stage pipeline acting as the controller for the eight SPEs, which handle most of the computational workload.The PPE will work with conventional operating systems due to its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating point code execution.IBM complied and made the tri-core Xenon processor, based on a slightly modified version of the PPE with added VMX128 extensions.[37][38] Each SPE is a dual issue in order processor composed of a "Synergistic Processing Unit",[39] SPU, and a "Memory Flow Controller", MFC (DMA, MMU, and bus interface).The local store does not operate like a conventional CPU cache since it is neither transparent to software nor does it contain hardware structures that predict which data to load.Compared to its personal computer contemporaries, the relatively high overall floating-point performance of a Cell processor seemingly dwarfs the abilities of the SIMD unit in CPUs like the Pentium 4 and the Athlon 64.[42] Tests by IBM show that the SPEs can reach 98% of their theoretical peak performance running optimized parallel matrix multiplication.[36] Toshiba has developed a co-processor powered by four SPEs, but no PPE, called the SpursEngine designed to accelerate 3D and movie effects in consumer electronics.IBM Senior Engineer David Krolak, EIB lead designer, explains the concurrency model: A ring can start a new op every three cycles.Despite IBM's original desire to implement the EIB as a more powerful cross-bar, the circular configuration they adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole.In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels.The IBM Systems Performance group explained: Each unit on the EIB can simultaneously send and receive 16 bytes of data every bus cycle.The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in the documentation set as yet made public by IBM.The IBM Systems Performance group has demonstrated SPU-centric data flows achieving 197 GB/s on a Cell processor running at 3.2 GHz so this number is a fair reflection on practice as well.Some companies, such as Leadtek, have released PCI-E cards based upon the Cell to allow for "faster than real time" transcoding of H.264, MPEG-2 and MPEG-4 video.Generating a measured 1.05 giga–floating point operations per second (gigaFLOPS) per watt, with peak performance of approximately 460 GFLOPS it is one of the most power efficient computing platforms to date.The QS22 introduces the PowerXCell 8i processor with five times the double-precision floating point performance of the QS21, and the capacity for up to 32 GB of DDR2 memory on-blade.In particular, the cluster performs astrophysical simulations of large supermassive black holes capturing smaller compact objects and has generated numerical data that has been published multiple times in the relevant scientific research literature.IBM announced on April 25, 2007, that it would begin integrating its Cell Broadband Engine Architecture microprocessors into the company's System z line of mainframes.[78] Terra Soft also maintains the Y-HPC (High Performance Computing) Cluster Construction and Management Suite and Y-Bio gene sequencing tools.Y-Bio is built upon the RPM Linux standard for package management, and offers tools which help bioinformatics researchers conduct their work with greater efficiency.[80][81] In November 2005, IBM released a "Cell Broadband Engine (CBE) Software Development Kit Version 1.0", consisting of a simulator and assorted tools, to its web site.Development versions of the latest kernel and tools for Fedora Core 4 are maintained at the Barcelona Supercomputing Center website.[83] In November 2007, Fixstars Corporation released the new "CVCell" module aiming to accelerate several important OpenCV APIs for Cell.
Toshiba64-bitPowerPC 2.02DesignLoad–storeEncodingBranchingCondition codeEndiannessBig/BiPowerPCPower ISAQorivvaPOWER1POWER2POWER3POWER4POWER5POWER6POWER7POWER8POWER9Power10RAD6000RAD750RAD5500BroadwayEspressoPWRficientOpenPOWER FoundationAIM allianceBlue GenePower.orgAltiVecmulti-coremicroprocessormicroarchitecturecoprocessingmultimediavector processingAustin, TexasPlayStation 3game consoleIBM RoadrunnersupercomputerTOP500LINPACKMercury Computer Systemsmemory coherencebandwidthlatencythroughputprogram codesoftware developmentPeter HofsteeSony Computer EntertainmentToshiba CorporationpatentsPower Processing ElementgigaFLOPS90 nm65 nmEast Fishkill, New YorkBandai Namco Entertainment45 nmPowerXCell 8iOpteronGreen500PlayStation 3 Slimthreadsdual threadedembeddedmedical imagingaerospacedefenseseismic processingtelecommunicationsbladesrack serversPCI Expressblade moduleAthlon 64Core 2NVIDIAonline distributiondigital imagingphysical simulationstructural engineeringsimultaneous-multithreadedcircular data busFourier analysisDMA (direct memory access)scratchpad memoryTuring completememory footprintmemory protectiongeneral-purpose registerBlade Serversdouble-precision floating-pointGFLOPSNEC SX-9AMD Opteronsingle precisiondouble precisionFixed Point Unit (FXU)Load and Store Unit (LSU)Floating-Point Unit (FPU)Branch Unit (BRU)MicrosoftXbox 360Xenon processorPowerPC e500branch predictioninstruction set128-bitembedded SRAM"Local Storage"CPU cacheregister fileset-top boxpersonal computerPentium 4branch predictorsco-processorSpursEngineconcurrency