Vector processor
Solomon's goal was to dramatically increase math performance by using a large number of simple coprocessors under the control of a single master Central processing unit (CPU).The CPU fed a single common instruction to all of the arithmetic logic units (ALUs), one per cycle, but with a different data point for each one to work on.This allowed the Solomon machine to apply a single algorithm to a large data set, fed in the form of an array.Nevertheless, it showed that the basic concept was sound, and, when used on data-intensive applications, such as computational fluid dynamics, the ILLIAC was the fastest machine in the world.Around this time Flynn categorized this type of processing as an early form of single instruction, multiple threads (SIMT).[2] The first vector supercomputers are the Control Data Corporation STAR-100 and Texas Instruments Advanced Scientific Computer (ASC), which were introduced in 1974 and 1972, respectively.However the machine also took considerable time decoding the vector instructions and getting ready to run the process, so it required very specific data sets to work on before it actually sped anything up.Control Data Corporation tried to re-enter the high-end market again with its ETA-10 machine, but it sold poorly and they took that as an opportunity to leave the supercomputing field entirely.In the early and mid-1980s Japanese companies (Fujitsu, Hitachi and Nippon Electric Corporation (NEC) introduced register-based vector machines similar to the Cray-1, typically being slightly faster and much smaller.Oregon-based Floating Point Systems (FPS) built add-on array processors for minicomputers, later building their own minisupercomputers.Modern graphics processing units (GPUs) include an array of shader pipelines which may be driven by compute kernels, and can be considered vector processors (using a similar strategy for hiding memory latencies).Although the exact internal details of today's commercial GPUs are proprietary secrets, the MIAOW[3] team was able to piece together anecdotal information sufficient to implement a subset of the AMDGPU architecture.(This can be somewhat mitigated by keeping the entire ISA to RISC principles: RVV only adds around 190 vector instructions even with the advanced features.However, as shown above and demonstrated by RISC-V RVV the efficiency of vector ISAs brings other benefits which are compelling even for Embedded use-cases.The only drawback is that in order to take full advantage of this extra batch processing capacity, the memory load and store speed correspondingly had to increase as well.to be a disadvantage of Cray-style vector processors: in reality it is part of achieving high performance throughput, as seen in GPUs, which face exactly the same issue.Modern SIMD computers claim to improve on early Cray by directly using multiple ALUs, for a higher degree of parallelism compared to only using the normal scalar pipeline.Modern GPUs, which have many small compute units each with their own independent SIMD ALUs, use Single Instruction Multiple Threads (SIMT).The Broadcom Videocore IV is also capable of this hybrid approach: nominally stating that its SIMD QPU Engine supports 16-long FP array operations in its instructions, it actually does them 4 at a time, as (another) form of "threads".[18] If it does not, a "splat" (broadcast) must be used, to copy the scalar argument across a SIMD register: The time taken would be basically the same as a vector implementation of y = mx + c described above.This more than triples the size of the code, in fact in extreme cases it results in an order of magnitude increase in instruction count!Without predication, the wider the SIMD width the worse the problems get, leading to massive opcode proliferation, degraded performance, extra power consumption and unnecessary software complexity.[19] Vector processors on the other hand are designed to issue computations of variable length for an arbitrary count, n, and thus require very little setup, and no cleanup.One additional potential complication: some RISC ISAs do not have a "min" instruction, needing instead to use a branch or scalar predicated compare.The hardware first defines how many data values it can process in one "vector": this could be either actual registers or it could be an internal loop (the hybrid approach, mentioned above).[tone] On calling setvl with the number of outstanding data elements to be processed, "setvl" is permitted (essentially required) to limit that to the Maximum Vector Length (MVL) and thus returns the actual number that can be processed by the hardware in subsequent vector instructions, and sets the internal special register, "VL", to that same amount.Also note, that just like the predicated SIMD variant, the pointers to x and y are advanced by t0 times four because they both point to 32 bit data, but that n is decremented by straight t0.Some vector ISAs offer a parallel reduction mode as an explicit option, for when the programmer knows that any potential rounding errors do not matter, and low latency is critical.Contrast this situation with SIMD, which is a fixed (inflexible) load width and fixed data processing width, unable to cope with loads that cross page boundaries, and even if they were they are unable to adapt to what actually succeeded, yet, paradoxically, if the SIMD program were to even attempt to find out in advance (in each inner loop, every time) what might optimally succeed, those instructions only serve to hinder performance because they would, by necessity, be part of the critical inner loop.This begins to hint at the reason why ffirst is so innovative, and is best illustrated by memcpy or strcpy when implemented with standard 128-bit non-predicated non-ffirst SIMD.
array processingcomputingcentral processing unitinstruction setinstructionsone-dimensional arraysscalar processorssingle instruction, multiple dataSIMD within a registernumerical simulationvideo-game consolegraphics acceleratorssupercomputerprice-to-performance ratiomicroprocessorWestinghouse Electric Corporationcoprocessorsarithmetic logic unitsalgorithmdata setUniversity of Illinois at Urbana–ChampaignILLIAC IVGFLOPScomputational fluid dynamicsmassively parallelsingle instruction, multiple threadsInternational Computers LimitedDistributed Array Processorcomputer for operations with functionsControl Data CorporationSTAR-100Texas InstrumentsAdvanced Scientific ComputerCDC 7600Cray-1vector registerspipeline parallelismvector chainingCray J90ETA-10FujitsuHitachiNippon Electric CorporationOregonFloating Point SystemsminicomputersminisupercomputersCray-2Cray X-MPCray Y-MPVirtual Vector ArchitectureSX seriesSX-Aurora TSUBASAshader pipelinescompute kernelsFlynn's 1972 paperAndes Technologyopen sourceLibre-SOC3DNow!ARM NEONPowerPCAltiVecToshibaCell processorARM SVE2AVX-512Convex C-SeriesNEC SXCDC STAR-100Fujitsu FR-Vpower of twoFlynn's taxonomymulti-issue execution modelmemory latencyinstruction pipeliningassembly lineaddress decoderlatencyembedded processorfunctional unitssupercomputersSingle Instruction Multiple ThreadsVideocoreprocessor registers"predicated"NEC SX-Aurora TSUBASAproperly alignedno-opspermute instructionsdata structurepredicate masksGather-scatterpermute instructionmapreduceGalois fieldbinary-coded decimalBit manipulationmany othersshadertrigonometricVulkanSPIR-Vmini-permute"swizzle"cosinelogarithmMIPS-3DSX architectureCompute kernelStream processingAutomatic vectorizationChaining (vector processing)RISC-VBarrel processorTensor Processing UnitHistory of supercomputingSupercomputer architectureGitHubPatterson, David A.Hennessy, John L.YouTubeParallel computingDistributed computingCloud computingHigh-performance computing