Instruction cycle
[1] The program counter (PC) is a register that holds the memory address of the next instruction to be executed.[2] Also, during a CPU halt, the PC holds the instruction being executed, until an external interrupt or a reset signal is received.For example, in RISC-V architecture, funct3 and funct7 opcodes exist to distinguish whether an instruction is a logical or arithmetic operation.The first instruction cycle begins as soon as power is applied to the system, with an initial PC value that is predefined by the system's architecture (for instance, in Intel IA-32 CPUs, the predefined PC value is 0xfffffff0 whereas for ARM architecture CPUs, it is 0x00000000.)Typically, this address points to a set of instructions in read-only memory (ROM), which begins the process of loading (or booting) the operating system.
- PC – Program counter
- MAR – Memory address register
- MDR – Memory data register
- CIR – Current instruction register
- CU – Control unit
- ALU – Arithmetic logic unit
central processing unitboot-upProgram counterMemory address registerMemory data registerCurrent instruction registerControl unitArithmetic logic unitconcurrentlyparallelinstruction pipelineCPU haltfloating-point unitopcodesRISC-V architectureinterruptsIntel IA-32ARM architectureread-only memorybootingoperating systemcontrol busdata busbinary decodersaddressing modesTime sliceClassic RISC pipelineComplex instruction set computerCycles per instructionBranch predictorInstruction set architectureProcessor technologiesModelsAbstract machineStored-program computerFinite-state machinewith datapathHierarchicalDeterministic finite automatonQueue automatonCellular automatonQuantum cellular automatonTuring machineAlternating Turing machineUniversalPost–TuringQuantumNondeterministic Turing machineProbabilistic Turing machineHypercomputationZeno machineStack machineRegister machinesCounterPointerRandom-accessRandom-access stored programArchitectureMicroarchitectureVon NeumannHarvardmodifiedDataflowTransport-triggeredCellularEndiannessMemory accessLoad–storeRegister/memoryCache hierarchyMemory hierarchyVirtual memorySecondary storageHeterogeneousFabricMultiprocessingCognitiveNeuromorphicInstruction setarchitecturesOrthogonal instruction setApplication-specificVISC architectureQuantum computingComparisonMotorola 68000 seriesPDP-11Stanford MIPSMIPS-XPowerPCPower ISAClipper architectureSuperHDEC AlphaETRAX CRISUnicoreItaniumOpenRISCRISC-VMicroBlazez/ArchitectureOthersInstruction pipeliningPipeline stallOperand forwardingHazardsData dependencyStructuralControlFalse sharingOut-of-orderScoreboardingTomasulo's algorithmReservation stationRe-order bufferRegister renamingWide-issueSpeculativeBranch predictionMemory dependence predictionParallelismBit-serialInstructionPipeliningScalarSuperscalarThread