POWER2

The POWER2, originally named RIOS2, is a processor designed by IBM that implemented the POWER instruction set architecture.The POWER2 was a multi-chip design consisting of six or eight semi-custom integrated circuits, depending on the amount of data cache (the 256 KB configuration required eight chips).It was a single-chip implementation of the eight-chip POWER2, integrating 15 million transistors on a 335 mm2 die manufactured in IBM's 0.29 μm five-layer metal CMOS-6S process.The P2SC was not a complete copy of the POWER2, the L1 data cache and data translation lookaside buffer (TLB) capacities were halved to 128 KB and 256 entries, respectively, and a rarely used feature that locked entries in the TLB was not implemented in order to fit the original design onto a single die.A notable use of the P2SC was the 30-node IBM Deep Blue supercomputer that beat world champion Garry Kasparov at chess in 1997.
The MCM of a POWER2 processor
A Power2+ MCM
A P2SC+
Instruction setPOWER ISAPOWER1POWER3PowerPCQorivvaPOWER4POWER5POWER6POWER7POWER8POWER9Power10RAD6000RAD750RAD5500BroadwayEspressoPWRficientOpenPOWER FoundationAIM allianceBlue GenePower.orgAltiVecprocessorinstruction set architectureRS/6000Alpha 21064GCC compilerfixed point unitfloating point unitmulti-chip moduletransaction processingwrite-throughsolder balltranslation lookaside bufferDeep BlueGarry Kasparovexpert systemIBM POWER Instruction Set ArchitectureIBM Power microprocessorsElectronics WeeklyElectronic NewsMicroprocessor ReportHot Chips 6