Memory-mapped I/O and port-mapped I/O

Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) are two complementary methods of performing input/output (I/O) between the central processing unit (CPU) and peripheral devices in a computer (often mediating access via chipset).I/O devices have a separate address space from general memory, either accomplished by an extra "I/O" pin on the CPU's physical interface, or an entire bus dedicated to I/O.One merit of memory-mapped I/O is that, by discarding the extra complexity that port I/O brings, a CPU requires less internal logic and is thus cheaper, faster, easier to build, consumes less power and can be physically smaller; this follows the basic tenets of reduced instruction set computing, and is also advantageous in embedded systems.However, even with address space being no longer a major concern, neither I/O mapping method is universally superior to the other, and there will be cases where using port-mapped I/O is still preferable.Lack of foresight in the choice of memory-mapped I/O regions led to many of the RAM-capacity barriers in older generations of computers.Designers rarely expected machines to grow to make full use of an architecture's theoretical RAM capacity, and thus often used some of the high-order bits of the address-space as selectors for memory-mapped I/O functions.The 3 GB barrier and PCI hole are similar manifestations of this with 32-bit address spaces, exacerbated by details of the x86 boot process and MMU design.Using the same method, graphs can be displayed on a screen by writing character values into a special area of RAM within the video controller.
Computer port (hardware)Memory-mapped fileProgrammed input–outputSaltillo Airportinput/outputcentral processing unitperipheral devicescomputerchipsetchannelsmainframe computersinstructionsaddress spacemain memoryI/O devicesregistersphysical RAMsystem bushardware registerbank switchingCommodore 64EAX registerdirect memory accessinterruptsreduced instruction set computingembedded systems16-bit32-bit64-bitx86-645 seriesDirect Media Interfacecacheswrite buffercache-flushing640 KB barrierUpper Memory Area3 GB barrierPCI holehexadecimalmicroprocessorkibibytesrandom access memoryread-only memoryaddress decoding circuitrymemory mapbit-mapped displaysText user interfaceaddress busaliasingPDP-11UnibusRalf Brown's Interrupt ListCoprocessorAdvanced Configuration and Power InterfaceSpeculative execution CPU vulnerabilitiesIBM PC compatibleMcGraw-Hill International Book CompanySpringer Science+Business MediaIntel CorporationAdvanced Micro DevicesMicrosoftHewlett-PackardProcessor technologiesModelsAbstract machineStored-program computerFinite-state machinewith datapathHierarchicalDeterministic finite automatonQueue automatonCellular automatonQuantum cellular automatonTuring machineAlternating Turing machineUniversalPost–TuringQuantumNondeterministic Turing machineProbabilistic Turing machineHypercomputationZeno machineStack machineRegister machinesCounterPointerRandom-accessRandom-access stored programArchitectureMicroarchitectureVon NeumannHarvardmodifiedDataflowTransport-triggeredCellularEndiannessMemory accessLoad–storeRegister/memoryCache hierarchyMemory hierarchyVirtual memorySecondary storageHeterogeneousFabricMultiprocessingCognitiveNeuromorphicInstruction setarchitecturesOrthogonal instruction setApplication-specificVISC architectureQuantum computingComparisonAddressing modesMotorola 68000 seriesStanford MIPSMIPS-XPowerPCPower ISAClipper architectureSuperHDEC AlphaETRAX CRISUnicoreItaniumOpenRISCRISC-VMicroBlazez/ArchitectureOthersExecutionInstruction pipeliningPipeline stallOperand forwardingClassic RISC pipelineHazardsData dependencyStructuralControlFalse sharingOut-of-orderScoreboardingTomasulo's algorithmReservation stationRe-order bufferRegister renamingWide-issueSpeculativeBranch predictionMemory dependence predictionParallelismBit-serialInstructionPipeliningScalarSuperscalarThreadProcessVectorMemoryDistributedMultithreadingTemporalSimultaneousHyperthreadingSimultaneous and heterogenousPreemptiveCooperativeFlynn's taxonomyArray processing (SIMT)ProcessorperformanceTransistor countInstructions per cycleCycles per instructionInstructions per secondFloating-point operations per secondTransactions per secondSynaptic updates per secondPerformance per wattCache performance metricsComputer performance by orders of magnitudeGraphics processing unitBarrelStreamTile processorMulti-chip moduleSystem in a packagePackage on a packageEmbedded systemMicrocontrollerMobileUltra-low-voltageSoft microprocessorSystem on a chipMultiprocessorCypress PSoCNetwork on a chipHardwareacceleratorsAI acceleratorImage processorVision processing unitPhysics processing unitDigital signal processorTensor Processing UnitSecure cryptoprocessorNetwork processorBaseband processorWord size12-bit15-bit24-bit48-bit128-bit256-bit512-bitbit slicingSingle-coreMulti-coreManycoreHeterogeneous architectureCPU cacheScratchpad memoryData cacheInstruction cachereplacement policiescoherenceClock rateClock signalFunctionalunitsArithmetic logic unitAddress generation unitFloating-point unitMemory management unitLoad–store unitTranslation lookaside bufferBranch predictorBranch target predictorIntegrated memory controllerInstruction decoderCombinationalSequentialLogic gateProcessor registerStatus registerStack registerRegister fileMemory bufferMemory address registerProgram counterControl unitHardwired control unitInstruction unitData bufferMicrocodeDatapathMultiplexerDemultiplexerMultiplierBinary decoderAddress decoderSum-addressed decoderBarrel shifterCircuitryIntegrated circuitMixed-signalPower managementBooleanDigitalAnalogPowermanagementDynamic frequency scalingDynamic voltage scalingClock gatingHistory of general-purpose CPUsMicroprocessor chronologyProcessor designDigital electronicsHardware security moduleSemiconductor device fabricationTick–tock modelPin grid arrayChip carrier