PowerPC 600

They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance.The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance.In order to achieve an extremely aggressive schedule while including substantially new functionality (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's first symmetric multiprocessing (SMP) implementation) the design leveraged a number of key technologies and project management strategies.From start of design to tape-out of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.The chip was designed to suit a wide variety of applications and had support for external L2 cache and symmetric multiprocessing.Thanks partly to the large cache it was considered a high performance processor in its segment, outperforming the competing Intel Pentium.The PowerPC 601 was used in the first Power Macintosh computers from Apple, and in a variety of RS/6000 workstations and SMP servers from IBM and Groupe Bull.IBM was the sole manufacturer of the 601 and 601+ microprocessors in its Burlington, Vermont and East Fishkill, New York production facilities.Introduced in 1994, it was an advanced design for its day, being one of the first microprocessors to offer dual issue (up to three with branch folding) and out-of-order execution combined with low power consumption of 2.2 W and a small die of 85 mm2.It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 120 MHz at 3.8 V.[10] The 603 core did not have hardware support for SMP.The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect.The PowerPC 603e is still sold today by IBM and Freescale, and others like Atmel and Honeywell who makes the radiation hardened variant RHPPC.The PowerPC 603e core, renamed G2 by Freescale, is the basis for many embedded PowerQUICC II processors, and, as such, it keeps on being developed.Freescale's PowerQUICC II SoC processors bear the designation MPC82xx, and come in a variety of configurations reaching 450 MHz.Freescale's PowerQUICC II Pro SoC processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667 MHz.The PowerPC 604 was introduced in December 1994 alongside the 603 and was designed as a high-performance chip for workstations and entry-level servers and as such had support for symmetric multiprocessing in hardware.The 604 was used extensively in Apple's high-end systems and was also used in Macintosh clones, IBM's low-end RS/6000 servers and workstations, Amiga accelerator boards, and as an embedded CPU for telecom applications.The PowerPC 604 contains 3.6 million transistors and was fabricated by IBM and Motorola with a 0.5 μm CMOS process with four levels of interconnect.[25][26] The PowerPC 604ev, 604r or "Mach 5" was introduced in August 1997 and was essentially a 604e fabricated by IBM and Motorola with a newer process, reaching higher speeds with a lower energy consumption.The sole user of PowerPC 620 was Groupe Bull in its Escala UNIX machines, but they didn't deliver any large numbers.The branch history table was also larger and could dispatch more instructions so that the processor can handle out-of-order execution more efficiently than the 604.[34][35][36] It supposedly was renamed "PowerPC 750" in response to Exponential Technology's x704 processor that was designed to outgun the 604 by a wide margin.Its main feature was to incorporate an x86 core on die, thus making the processor able to natively process both PowerPC and x86 instructions.With progress having been demonstrated in the development of dynamic translation software, such as Digital's FX!32 technology, skepticism was expressed about dedicating hardware resources to running foreign binaries when such resources could be used to improve native performance instead, this also benefiting the performance of translated binaries.