CDC Cyber

The Cyber line included five different series of computers: Primarily aimed at large office applications instead of the traditional supercomputer tasks, some of the Cyber machines nevertheless included basic vector instructions for added performance in traditional CDC roles.In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors).A Cyber 170-series system consists of one or two CPUs that run at either 25 or 40 MHz, and is equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed I/O.Any loop that fit into the cache (which is usually called in-stack) runs very fast, without referencing main memory for instruction fetch.The higher-end CPUs consisted of multiple functional units (e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions.With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer can write extremely efficient code that makes the most of the power of the hardware.The PP instruction set lacks, for example, extensive arithmetic capabilities and does not run user code; the peripheral processor subsystem's purpose is to process I/O and thereby free the more powerful central processor unit(s) to running user computations.Besides NOS, the only other operating systems commonly used on the 170 series was NOS/BE or its predecessor SCOPE, a product of CDC's Sunnyvale division.Other installations would patch newer versions of the operating system to use the older character set to maintain application compatibility.As the computing world standardized to an eight-bit byte size, CDC customers started pushing for the Cyber machines to do the same.The P1 was a novel air-cooled, 60-board cabinet designed by a group in Mississauga; the P1 ran on 60 Hz current (no motor-generator sets needed).There were a few clues that an alert user could pick up on, such as the "building page tables" message that flashed on the operator's console at startup and deadstart panels with 16 (instead of 12) toggle switches per PP word on the P2 and P3.The 825 was released initially after some delay loops had been added to its microcode; it seemed the design folks in Toronto had done a little too well and it was too close to the P2 in performance.The STAR is an entirely new 64-bit design with virtual memory and vector processing instructions added for high performance on a certain class of math tasks.The Cyber 203 contains redesigned scalar processing and loosely coupled I/O design,[a] but retains the STAR's vector pipeline.A final development was the Cyber 250, which was scheduled for release in 1987 priced at $20 million; it was later renamed the ETA30 after ETA Systems was absorbed back into CDC.The AFP was the successor to the Flexible Processor (FP), whose design development started in 1972 under black-project circumstances targeted at processing radar and photo image data.Physically, each Cyberplus processor unit was of typical mainframe module size, similar to the Cyber 180 systems,[12] with the exact width dependent on whether the optional FPU was installed, and weighed approximately 1 tonne.Some sites using the Cyberplus were the University of Georgia and the Gesellschaft für Trendanalysen (GfTA) (Association for Trend Analyses) in Germany.A fully configured 256 processor Cyberplus system would have a theoretical performance of 64 GFLOPS, and weigh around 256 tonnes.The Cyber 18 was generally programmed in Pascal and assembly language; FORTRAN, BASIC, and RPG II were also available.The Bell Operating Companies purchased large numbers of these systems in the mid-to-late 1980s for data communications.In the late 1980s the XN10 was released with an improved processor (a direct memory access instruction was added) as well as a size reduction from two cabinets to one.