The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments.When presented at the '97 Microprocessor Forum, the probable introduction date for the UltraSPARC III was 1999, and it would have competed with Digital Equipment Corporation's Alpha 21264 and Intel's Itanium (Merced).This increases bandwidth for accessing the cache tags, enabling the UltraSPARC to scale to higher clock frequencies easily.Unlike most other microprocessors bonded in such a way, the majority of the solder bumps are placed in a peripheral ring instead of being distributed across the die.It has a die size of 232 mm2 and was fabricated in a 0.13 μm, 7-layer copper metallization, CMOS process by Texas Instruments.It operates at 1064 to 1593 MHz, has an on-die L2 cache and an integrated memory controller, and is capable of four-way multiprocessing with a glue-less system bus optimized for the function.It was fabricated by Texas Instruments in a 0.13 μm, seven-layer metal (copper) CMOS process with low-k dielectric.Improvements were higher clock frequencies in the range of 2 GHz, a larger (4 MB) on-die L2 cache, support for DDR-333 SDRAM, and a new 90 nm process.The CPU's packaging was nearly identical, offering the difference of a single pin, simplifying board manufacturing and system design.