SPARC64 V

The SPARC64 VI and its successors up to the VII+ were used in the Fujitsu and Sun (later Oracle) SPARC Enterprise M-Series servers.Fujitsu's 2003 SPARC64 roadmap showed that the company planned a 1.62 GHz version for release in late 2003 or early 2004, but it was canceled in favor of the SPARC64 V+.Its purpose is reduce the size of register file so that the microprocessor can operate at higher clock frequencies.Loads and stores are executed by two address generators (AGs) designated AGA and AGB.Unlike its successor SPARC64 VI, the SPARC64 V performs the multiply–add with separate multiplication and addition operations, thus with up to two rounding errors.[10] It was fabricated in a 0.13 μm,[11] eight-layer copper metallization, complementary metal–oxide–semiconductor (CMOS) silicon on insulator (SOI) process.It is fabricated by Fujitsu in a 90 nm, 10-layer copper, CMOS silicon on insulator (SOI) process, which enabled two cores and an L2 cache to be integrated on a die.[15] The addition of CMT required duplication of the program counter and the control, integer, and floating-point registers so there is one set of each for every thread.A floating-point fused multiply-add (FMA) instruction was also added, the first SPARC processor to do so.Development of the PrimerPowers were canceled after Fujitsu and Sun Microsystems announced in June 2004 that they would collaborate on new servers called the Advanced Product Line (APL).[16] The SPARC64 VII (previously called the SPARC64 VI+),[17] code-named Jupiter,[18] is a further development of the SPARC64 VI announced in July 2008.[19] Other changes include more RAS features; the integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400.SPARC64 VIIs could coexist, whilst operating at their native clock frequency, alongside SPARC64 VIs.Existing high-end SPARC Enterprise M-Series servers are able to upgrade to the VII+ processors in the field.[28] The SPARC64 VIIIfx (Venus) is an eight-core processor based on the SPARC64 VII designed for high-performance computing (HPC).It consists of 760 million transistors, measures 22.7 mm by 22.6 (513.02 mm2;), is fabricated in Fujitu's 45 nm CMOS process with copper interconnects, and has 1,271 I/O pins.The VIIIfx has a peak performance at 2 GHz of 128 GFLOPS and a typical power consumption of 58 W at 30 °C for an efficiency of 2.2 GFLOPS/W.The supercomputer was originally envisioned to have a hybrid architecture containing scalar and vector processors.Located at the RIKEN's Advanced Institute for Computational Science (AICS) in Kobe, Japan;[31][32][33] it obtains its performance from 88,128 VIIIfx processors.In June 2011, the TOP500 Project Committee announced that the K computer (still incomplete with only 68,544 processors) topped the LINPACK benchmark at 8.162 PFLOPS, realizing 93% of its peak performance, making it the fastest supercomputer in the world at that time.The front-end had coarse-grained multi-threading removed, the L1 instruction cache halved in size to 32 KB; and the number of branch target address cache (BTAC) entries reduced to 1,024 from 8,192, and its associativity reduced to two from eight; and an extra pipeline stage was inserted before the instruction decoder.The number of load queue entries was increased to 20 from 16, and the L1 data cache was halved in size to 32 KB.The SPARC64 IXfx is an improved version of the SPARC64 VIIIfx designed by Fujitsu and LSI[37] first revealed in the announcement of the PRIMEHPC FX10 supercomputer on 7 November 2011.The cores were improved by the inclusion of a pattern history table for branch prediction, speculative execution of loads, more execution units, support for the HPC-ACE extension (originally from the SPARC64 VIIIfx), deeper pipeline for a 3.0 GHz clock frequency, and accelerators for cryptography, database, and decimal floating-point number arithmetic and conversion functions.Chip organization improvements include four integrated DDR3 SDRAM memory controllers, glueless four-way symmetrical multiprocessing, ten SERDES channels for symmetrical multiprocessing scalability to 64 sockets, and two integrated PCI Express 3.0 controllers.It features minor improvements to the core organization, and a higher 3.5 GHz clock frequency obtained through better circuit design and layout.[48] It consists of 3.75 billion transistors and is fabricated by the Taiwan Semiconductor Manufacturing Company in its 20 nm high-κ metal gate (HKMG) process.Tofu2 is a 6D mesh/torus network with a 25 GB/s full-duplex bandwidth (12.5 GB/s per direction, 125 GB/s for ten ports) and an improved routing architecture.The size of the chip is 25.8mm × 30.8mm (795mm2), containing 5.45 billion transistors made on TSMC's 20 nm process.Memory speed has been increased by 50% to 2400 MT/s, bringing the theoretical combined bandwidth of the 8 DDR4 channels of the chip to 153 GB/s, and the capacity per CPU is up to 1.5 TB across 24 slots.