Planar process

It is the primary process by which silicon integrated circuit chips are built, and it is the most commonly used method of producing junctions during the manufacture of semiconductor devices.The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion.[5][6][7][8] Later, Hoerni attended a meeting where Atalla presented a paper about passivation based on the previous results at Bell Labs.[9][10] K. E. Daburlos and H. J. Patterson of Bell Laboratories continued on the work of C. Frosch and L. Derick, and developed a process similar to Hoerni’s about the same time.In 1959, Robert Noyce built on Hoerni's work with his conception of an integrated circuit (IC), which added a layer of metal to the top of Hoerni's basic structure to connect different components, such as transistors, capacitors, or resistors, located on the same piece of silicon.
Annotated die photo of a Fairchild chip
manufacturing processsemiconductor industrytransistorsiliconintegrated circuitjunctionssemiconductor devicessurface passivationthermal oxidationFairchild Semiconductorphotographic processingsilicon oxidep–n junction isolationsilicon dioxideoxidizingBell LabsCarl FroschShockley SemiconductorJean HoerniAtallaKurt Lehovecmonocrystalline siliconRobert Noycecapacitorsresistorsphotolithographyextreme ultraviolet lithographySemiconductor device fabricationJohn Wiley & SonsThe Electrochemical SocietySpringer Science & Business MediaJohns Hopkins University PressComputer History Museumintegrated circuits