R10000
The R10000 was not available in large volumes until later in the year due to fabrication problems at MIPS's foundries.[1] On 25 September 1996, SGI announced that R10000s fabricated by NEC between March and the end of July that year were faulty, drawing too much current and causing systems to shut down during operation.Users of the R10000 include: The R10000 is a four-way superscalar design that implements register renaming and executes instructions out-of-order.The adder has its own dedicated read and write ports, whereas the multiplier shares its with the divider and square root unit.The cache is two-way set associative, but to avoid a high pin count, the R10000 predicts which way is accessed.MIPS IV is a 64-bit architecture, but to reduce cost the R10000 does not implement the entire physical or virtual address.The system interface controller supports glue-less symmetrical multiprocessing (SMP) of up to four microprocessors.It is fabricated in a 0.35 μm process and packaged in 599-pad ceramic land grid array (LGA).All derivatives after the R12000 have their clock frequency kept as low as possible to maintain power dissipation in the 15 to 20 W range so they can be densely packaged in SGI's high performance computing (HPC) systems.The R12000 was fabricated by NEC and Toshiba in a 0.25 μm CMOS process with four levels of aluminum interconnect.Introduced in July 2000, it operates at 400 MHz and was fabricated by NEC a 0.18 μm process with aluminum interconnects.The R14000 operates at 500 MHz, enabled by the 0.13 μm CMOS process with five levels of copper interconnect it is fabricated with.It features improvements to the microarchitecture of the R12000 by supporting double data rate (DDR) SSRAMs for the secondary cache and a 200 MHz system bus.It operates at 600 MHz, dissipates approximately 17 W, and was fabricated by NEC Corporation in a 0.13 μm CMOS process with seven levels of copper interconnect.The R18000 is a canceled further development of the R10000 microarchitecture that featured major improvements by Silicon Graphics, Inc. described at the Hot Chips symposium in 2001.The R18000 would have a 1 MB four-way set-associative secondary cache to be included on-die; supplemented by an optional tertiary cache built from single data rate (SDR) or double data rate (DDR) SSRAM or DDR SDRAM with capacities of 2 to 64 MB.It would have used 1.2 V power supply and dissipated less heat than contemporary server microprocessors in order to be densely packed into systems.
MIPS IVinstruction set architectureMIPS Technologies, Inc.Silicon Graphics, Inc.microarchitecturefabless semiconductor companyToshibaIntegrated Device TechnologyIndigo2OctaneChallengeOrigin 2000Siemens NixdorfTandem Computerssuperscalarregister renamingout-of-orderscalaroperandsregister filepipelinesbarrel shifternon-restoring algorithmfloating-point unitreciprocal square rootsingle precisiondouble precisionfused multiply–addset-associativewrite-backcoherencysynchronousstatic random access memoryerror correcting codevirtual addressphysical addressphysical memoryvirtual memorymultiplexedsymmetrical multiprocessingland grid arrayMicroprocessor Reportmulti-chip modulehigh performance computingSiemens-Nixdorfaluminum interconnectaluminum interconnectscopper interconnectdouble data rateNEC CorporationOrigin 350Origin 3000NonStop Himalaya S-SeriesIEEE MicroThe RegisterPress releaseByte MagazineCNET NewsMIPS architectureMIPS architecture processorsList of MIPS architecture processorsIngenic XBurstBen NanoNoteSkytone Alpha-400Dingoo A320Game GadgetAinol Novo7 PaladinMicrocontrollersMicrochip TechnologyXilleonQualcomm AtherosMediaTekTexas InstrumentsLantiqMarvellIkanosBroadcomRealtekCaviumAlchemyRMI CorporationPlayStation 1Nintendo 64PlayStation PortablePlayStation 2Emotion EngineSupercomputerLoongson-based systemsSiCortexMIPS IMIPS IIMIPS IIIMIPS V